For image processing, filtering engines require random access to memory due to the fact that images are at least two dimensional. The term random access means that the system can access any data value inside the memory. Burst memory devices (such as DRAM, SDRAM and DDR memory) do not provide random access in burst mode. Burst mode refers to memories which provide data access in groups (i.e. bursts) of data as opposed to single data values. Burst-based memories are used more and more in today's data intensive applications.
As an example, assuming there is a memory with burst size of 16 pixels across, and data from it is required for vertical processing, if a non buffering technique is employed as data is being read row-wise, every 16th pixel that is read would be a pixel that would be required for vertical processing for one particular column. For the processing engine to only make use of every 16th pixel that is read out is extremely inefficient.
Current art when addressing this problem of trying to increase efficiency, employs a cache storage technique to ensure that the required data for processing is always available. Caching is a viable solution to the problem, but is marred by significantly increased complexity. Caching techniques require among other things, that checks be done to determine cache misses as well as data coherency checking, all of which result in increased complexity.
Patents such as U.S. Pat. No. 5,859,651 to Potu have attempted to deal with the issues surrounding image processing. This patent employs concepts such as FIFO (First-in First out Buffers), as well as block dimensions which are square, for when the data is being processed. Also, the filtering process that is employed with U.S. Pat. No. 5,859,651 is one that requires data that is to be processed to be resent between blocks that are being processed. As a result, the system may not be utilized as efficiently as one would like.